The present invention relates generally to signal generators and more specifically to a signal generator that can accurately control phase relationships between output signal channels and provide faster output signals.
During the design of electronic devices, some of the circuits in the device are produced as prototype circuits but other circuits in the device may not have been completed. In such a case, a signal generator can be used to simulate the output of the preceding circuit stage for confirming the operation of the prototype circuit by providing the simulated signals to the prototype circuit.
Some prototype circuits require multiple stimulation signal to be provided to points of the circuit. Therefore, some the signal generators have multiple signal output channels providing synchronized signal outputs between the channels. The signal outputs of the channels may be started by a user initiating an output start operation of the signal generator. The signal generator may receive an external trigger signal and start providing signal outputs from the channels in response to the trigger signal. U.S. Pat. No. 6,356,224 discloses a signal generator having multiple signal output channels.
A typical signal generator has a signal generation block having a waveform memory and digital to analog converter (DAC). The waveform memory stores waveform data representing the output signals. The user can edit the waveform data if necessary. The DAC converts the waveform data into an analog signal output. If the signal generator has multiple signal channels, each of the channels has a signal generation block with the waveform memory being shared by the signal generator blocks.
FIG. 1 is a functional block diagram of a conventional signal generator having multiple signal channels. A start signal is provided to a flip-flop (FF) 18 that controls the ON/OFF status of gate 16. The start signal is provided by a control means that preferably includes a microprocessor, hard disk drive, operation panel, and the like. The start signal is controlled by the control means in response to user input settings. If the start signal transitions from low to high, the Q output of the FF 18 becomes high at the next rising edge of the clock to turn the gate 16 “ON” so that the clock is provided to first and second signal generation blocks 10 and 12 on the next rising edge of the clock. On the other hand, if the start signal transitions from high to low, the Q output of the FF 18 becomes low at the next rising edge of the clock to turn the gate 16 “OFF” so that the clock stops being provided to the first and second signal generation blocks 10 and 12 on the next rising edge of the clock. The signal generator provides signal outputs from the channels at the same time in response to in phase clocks. This signal generator synchronizes the outputs of first and second signal generation blocks 10 and 12 through controlling the clocks that are operation reference for the first and second signal generation blocks 10 and 12. That is, the AND gate 16 controls the clock from a clock oscillator 14 whether it is provided or not to the first and second signal generation blocks 10 and 12.
At slow clock speeds, the synchronization between the channels by the clocks to the signal blocks as shown in FIG. 1 is stable. However if the clock speed is over 100 MHz the operation becomes unstable. This is because rectangular shape of a clock pulse becomes close to a sine wave and when the circuit resumes providing the clock the duty ratio of the clock pulse breaks, and then the logic circuits sometimes recognize the fist clock pulse and sometimes not. As the operating speeds of electronic devices increase, there is a need for signal generators to generate output signal with higher frequencies.
PLL (Phase lock loop) or DLL (Delayed Lock Loop) may be used to make the circuit operation faster. The DLL intentionally delays the clock phase up to one period at the maximum to align phases so that there is no delay. But this process cannot be used if the clock is not continuously provided.
Therefore what is desired is to provide stable operation of synchronized signal outputs of channels at faster clock speeds. It is further desirable to provide signal outputs from the channels with user defined phase differences in addition to simultaneous signal outputs. It is also desirable to provide faster signal outputs from the channels.